The device size is required to be scaled down as the IC integration level constantly increases. In order to solve a series of problems caused by scaling down of the MOS device, the traditional SiO2/polysilicon gate structure is generally substituted by the high-K/metal gate stack structure. Currently, the process for manufacturing a semiconductor device with a high-K/metal gate structure is mainly divided into a gate first process and a gate last process. The gate first process is first to manufacture the high-K/metal gate stack structure, and then to perform the source/drain implantation, whereas the gate last process is first to perform the source/drain implantation, and then to form the high-K/metal gate stack structure. Presently, the gate last process is gradually accepted in the industry since it is unnecessary for the gate last process to introduce high temperature for source/drain annealing.
In such a gate last process, generally, a dummy gate made of silicon-based materials such as polysilicon, microcrystalline silicon, and amorphous silicon is formed on the substrate. After performing etching to form a dummy gate stack structure, a source/drain doping implantation is performed with the dummy gate stack structure as a mask. Then, after depositing an interlayer dielectric layer, the dummy gate stack structure is removed by etching to result in a gate trench, in which a high-K material and a metal gate material are deposited. Since the dummy gate is made of a material similar to that of the substrate, both of which are made of silicon-based materials, the substrate will be inevitably overetched in the process of etching the dummy gate, resulting in an increase in the defect density in the surface of the channel region of the substrate, and thus the electrical performance and reliability of the device are degraded. Accordingly, an oxide liner (made of silicon oxide and high-K materials etc. with a general thickness of about 3 nm only) and/or an etch blocking layer (generally made of refractory-metal nitrides such as TiN and TaN with a thickness of about, e.g., 1 nm) must be formed on the substrate, and the channel region in the substrate can be protected by using the oxide liner and/or the etch blocking layer.
However, the oxide liner and/or the etch blocking layer has an ultra-thin thickness, so it is hard to be formed uniformly. As a result, the substrate may also be partially overetched during the process of etching to form a gate trench. Besides, formation of such an ultra-thin oxide liner and/or etch blocking layer involves complicated processes and expensive materials, hence it is hardly applicable to mass manufacture of the device, and it is difficult to improve efficiency and reduce cost effectively.
In summary, in the prior art it is difficult to protect the substrate from overetching in the gate last process with high efficiency and low cost.